The VS EtherCAT Master starting with version 2.4 supports the function "Hardware timed send". It enables the cyclic frame to be sent exactly at the beginning of the Master cycle without any delays. Usually, the Master starts preparing the cyclic frame at the beginning of the Master cycle. As a result, the actual time of frame transmission is delayed by the time of preparation.
The hardware-timed send function can only be activated if the target system has a hardware timer. With hardware-controlled sending enabled, the Master prepares the frames in advance before starting the cycle and transfers them to a hardware module (HW module) on the target. Therefore, when the cycle starts, the HW module just sends the prepared frames without delay. The function is applicable for target systems developed based on the Xilinx Zynq SoC / Zynq UltraScale+ MPSoC family, Intel FPGA Cyclone V SoC and Texas Instruments Sitara AM437x/AM57x. The function is licensed as an additional product feature.
Timed send emulation
If the target system does not include a hardware timer, the hardware timed send function cannot be enabled, but a software emulation of it can be used. Timed send emulation makes it possible to imitate the timed send functionality. Both the emulation and the hardware-assisted timed send minimize jitter when sending cyclic frames.
With the emulation of timed sending enabled, the Master also prepares the frames before the cycle starts and passes them to a separate thread (instead of the HW module). It sends as soon as the cycle begins.
This function is included in all Master classes and requires no additional licensing.
